PLL circuits find use in a variety of applications such as in the demodulation of frequency- and phase-modulated signals, frequency conversion, carrier regeneration and signal synchronization such as clock synchronization and timing extraction. An example of a PLL circuit according to the prior art will be described below.
FIG. 10 is a block diagram illustrating an example of the structure of a conventional PLL circuit. As shown in FIG. 10, the PLL circuit includes a voltage-controlled oscillator (VCO) 40′ which oscillates at a frequency conforming to a control voltage applied thereto; a frequency divider 50 for frequency-dividing the output signal of the voltage-controlled oscillator 40′; a phase comparator 10, to which an input signal IN and an output signal OUT from the frequency divider 50 are input, for comparing the phases of these input signals and outputting an UP signal and a DOWN signal having pulse widths that correspond to the result of the phase comparison; a charge pump (CP) 20′, which charges and discharges a capacitor in accordance with the UP and DOWN signals output from the phase comparator 10, for generating a voltage conforming to the phase difference between the input signal N and the output signal OUT; and a loop filter 30′ comprising a low-pass filter (LPF) having a low-pass characteristic that blocks high-frequency components from the output voltage of the charge pump 20′. The output voltage of the 30′ is input to the voltage-controlled oscillator 40′ as the control voltage.
FIG. 11 is a diagram useful in describing the structures of the charge pump 20′ and voltage-controlled oscillator 40′. When the UP signal output from the phase comparator 10 is in the active state in FIG. 11, a first switch 202 in the charge pump 20′ having the UP signal input to its control terminal is closed. As a result, a constant current from a first constant-current source 201, which is connected between a high-potential power supply (VDD) and one end of the first switch 202 and outputs a source current, is charged in a capacitor 205 having its one end connected to the other end of the first switch 202 and its other end connected to a low-potential power supply (GND). This causes the terminal voltage of the capacitor 205 to rise. The terminal voltage of the capacitor 205 is input as a control voltage to a non-inverting input terminal (+) of the voltage-control led oscillator 40′ via a loop filter (not shown). Owing to the rise in the terminal voltage of the capacitor 205, control is performed in such a manner that the oscillation frequency of the voltage-control led oscillator 40′ rises so that the phase of the output signal OUT of frequency divider 50 applied to the phase comparator 10 of FIG. 10 is advanced and approaches the phase of input signal IN.
On the other hand, when the DOWN signal output from the phase comparator 10 is in the active state, a second switch 203 having the DOWN signal input to its control terminal and having one end thereof connected to one end of the capacitor 205 is closed. As a result, the capacitor 205 is discharged by a constant current from a second constant-current source 204, which is connected between the low-potential power supply (GND) and the other end of the second switch 203. This causes the terminal voltage of the capacitor 205 to fall. Owing to the fall in the terminal voltage of the capacitor 205, control is performed in such a manner that the oscillation frequency of the voltage-control led oscillator 40′ declines so that the phase of the output signal OUT of frequency divider 50 applied to the phase comparator 10 is delayed and approaches the phase of input signal IN.
Thus, in the PLL circuit shown in FIG. 10, the terminal voltage of the capacitor 205 (see FIG. 11) varies in dependence upon the UP and DOWN signals output from the phase comparator 10, as a result of which the output signal OUT and input signal IN from the frequency divider 50 are subjected to phase synchronization control.
With reference again to FIG. 11, the voltage-controlled oscillator 40′ includes a voltage-to-current converter (V/I) 41 and a current-controlled oscillator (ICO) 42. The voltage-to-current converter 41, which has a non-inverting input terminal (+) connected to the non-inverting input terminal (+) of the voltage-control led oscillator 40′, receives the terminal voltage of the capacitor 205, namely the output terminal voltage of the loop filter 30′, as its input, has a reference voltage (Vref) of a preset fixed potential supplied to an inverting input terminal (−) outputs a current corresponding to the difference voltage between the voltage applied to the non-inverting input terminal (+) and the reference voltage Vref. The current-controlled oscillator 42, to which the output current of the voltage-to-current converter 41 is input as a control current, oscillates at a frequency that conforms to the above-mentioned control current.
FIG. 12 is a diagram illustrating an example of the circuit structure of the charge pump 20′ in this PLL circuit. As shown in FIG. 12, the charge pump 20′ has P-channel MOS transistors PM1, PM2 and PM3 the sources whereof are connected to the high-potential power supply (VDD). The gate and drain of the P-channel MOS transistor PM2 are connected, the gate of the P-channel MOS transistor PM3 and the gate of the P-channel MOS transistor PM2 are connected together, the UP signal output from the phase comparator 10 is input to the gate of the P-channel MOS transistor PM1, and the drain of the P-channel MOS transistor PM1 is connected to the common-connected gates of the P-channel MOS transistors PM2 and PM3.
The charge pump 20′ further includes N-channel MOS transistors NM1, NM2 and NM3 the sources whereof are connected to the low-potential power supply (GND). The gate and drain of the N-channel MOS transistor NM2 are connected, the gate of the N-channel MOS transistor NM3 and the gate of the N-channel MOS transistor NM2 are connected together, the DOWN signal output from the phase comparator 10 is input to the gate of the N-channel MOS transistor NM1, and the drain of the N-channel MOS transistor NM1 is connected to the common-connected gates of the N-channel MOS transistors NM2 and NM3.
The drain of the P-channel MOS transistor PM2 is connected to the output terminal of a first constant-current source 21, the drain of the N-channel MOS transistor NM2 is connected to the output terminal of a first constant-current source 22, and the drain of the P-channel MOS transistor PM3 and the drain of the N-channel MOS transistor NM3 are connected together and further connected to the input terminal of the loop filter 30′ and to the non-inverting input terminal (+) of the voltage-controlled oscillator 40′.
The P-channel MOS transistors PM2, PM3 construct a first current mirror circuit 23 and the N-channel MOS transistors NM2, NM3 construct a second current mirror circuit 24. When the P-channel MOS transistor PM1 turns on (i.e. when the UP signal is at the high level), the first current mirror circuit 23 reflects the current value of the first constant-current source 21 supplied to the drain of the P-channel MOS transistor PM2 serving as the input terminal to this mirror circuit, whereby the current value is output from the drain of the P-channel MOS transistor PM3 serving as the output terminal. When the N-channel MOS transistor NM1 turns on (i.e., when the DOWN signal is at the low level), the second current mirror circuit 24 reflects the current value of the second constant-current source 22 supplied to the drain of the N-channel MOS transistor NM2 serving as the input terminal to this mirror circuit, whereby the current value is output from the drain of the N-channel MOS transistor NM3 serving as the output terminal.
In the circuit arrangement shown in FIG. 12, the loop filter 30′ includes a capacitor C0 charged and discharged by the charge pump 20′ and the terminal voltage of which forms the output terminal voltage of the loop filter 30′. It goes without saying that a low-pass filter of a desired characteristic or construction may be provided across one end of the capacitor C0 charged and discharged by the charge pump 20′ and the non-inverting input terminal (+) of the voltage-controlled oscillator 40′.
In response to the UP signal supplied by the phase comparator 10, the current from the first constant-current source 21 of charge pump 20′ is reflected by the first current mirror circuit 23 and a current P from the P-channel MOS transistor PM3 is supplied to the capacitor of the loop filter 30′ the output terminal of which is connected to the non-inverting input terminal (+) of the voltage-controlled oscillator 40′. In response to the DOWN signal supplied by the phase comparator 10, the constant current from the second constant-current source 22 is reflected by the second current mirror circuit 24 and a current N from the N-channel MOS transistor NM3 is supplied to the capacitor of the loop filter 30′ the output terminal of which is connected to the non-inverting input terminal (+) of the voltage-controlled oscillator 40′. The oscillation frequency of the voltage-control led oscillator 40′ rises and falls in dependence upon the rise and fall of the terminal voltage impressed upon the non-inverting input terminal (+).
The phase comparator 10 again compares the phases of the input signal IN and of the output signal OUT, which is obtained by frequency-dividing, by the frequency divider 50, the output signal from the voltage-controlled oscillator 40′ the oscillation frequency whereof has risen or fallen in conformity with the control voltage input thereto. The phase comparator 10 produces and outputs the UP and DOWN signals in accordance with the result of the phase comparison.
FIGS. 13A, 13B and 13C are diagrams illustrating an example of the structure of the voltage-control led oscillator 40′. FIG. 13A is a diagram showing an example of the structure of the voltage-to-current converter 41 depicted in FIG. 11. As shown in FIG. 13A, the voltage-to-current converter has P-channel MOS transistor PM42 and PM42 the sources of which are connected together and further connected to a constant-current source I0 which supplies a reference current, and the gates of which have an output voltage (Vin) of the loop filter (LPF) 30′ that enters from the non-inverting input terminal (+) and the reference voltage (Vref) supplied to the inverting input terminal (−), respectively, input thereto. The drain of the P-channel MOS transistor PM41 is connected to the low-potential power supply (GND), the drain of the P-channel MOS transistor PM42 is connected to the drain of an N-channel MOS transistor NM41 whose source is connected to GND potential and whose drain and gate are connected together, and a current is output from the drain of an N-channel MOS transistor NM41 whose drain is connected to the gate of the N-channel MOS transistor NM41 and whose source is connected to GND potential. The N-channel MOS transistors NM41 and NM42 construct a current mirror circuit. A drain current corresponding to a difference voltage between the input voltage (control voltage) Vin from the non-inverting input terminal (+) and the reference voltage (Vref) is output from the P-channel MOS transistor PM42 and applied to the input terminal of the current mirror circuit. The mirror current is output from the drain of the N-channel MOS transistor NM42, which forms the output terminal of the current mirror, as a control current Iout for the current-controlled oscillator.
When the input voltage (Vin) from the non-inverting input terminal (+) and the reference voltage (Vref) are equal, the drain current of the P-channel MOS transistor PM42 becomes one-half the constant current I0, the control current Iout becomes I0/2 and the voltage-controlled oscillator 40′ oscillates at a center frequency of the range of oscillation frequencies.
When the input voltage (Vin) from the non-inverting input terminal (+) is greater than the reference voltage (Vref), the drain current that flows into the P-channel MOS transistor PM41 becomes smaller than I0/2, the drain current that flows into the P-channel MOS transistor PM42 becomes larger than I0/2 and the oscillation frequency of the voltage-control led oscillator 40′ becomes higher than the center frequency thereof.
When the input voltage (Vin) from the non-inverting input terminal (+) is smaller than the reference voltage (Vref), on the other hand, the drain current that flows into the P-channel MOS transistor PM41 becomes larger than I0/2, the drain current that flows into the P-channel MOS transistor PM42 becomes smaller than I0/2 and the oscillation frequency of the voltage-controlled oscillator 40′ falls below the center frequency thereof.
FIG. 13B is a diagram illustrating an example of the structure of the current-controlled oscillator (ICO) 42. As shown in FIG. 13B, the current-control led oscillator 42 includes a P-channel MOS transistor PM43 whose source is connected to the high-potential power supply (VDD) and whose gate and drain are connected together and further connected to a control-current input terminal; a ring oscillator comprising an odd number (three in the illustrated example) of inverters 301, 302, 303 and having its output terminals connected to its input terminals; and a voltage comparator 304 which produces an output signal (the ICO output) upon receiving the differential voltage output of the final stage inverter 303 of the ring oscillator.
FIG. 13C is a diagram illustrating an example of the circuit construction of the inverters constituting the ring oscillator of the current-controlled oscillator 42. As shown in FIG. 13C, each inverter comprises a differential amplifier circuit having a P-channel MOS transistor PM44 the source and gate of which are connected to a power supply and to a G terminal, respectively, and which acts as constant-current source; and P-channel MOS transistors PM45 and PM46 the sources of which are connected together and to the drain of the P-channel MOS transistor PM44, the gates of which are connected to differential input terminals 11, 12, respectively, and the drains of which are connected to the GND potential via load resistors R1, R2, respectively, and to differential output terminals 01, 02, respectively. The G terminal of the inverter is connected to the gate of the P-channel MOS transistor PM43. That is, the input control current is converted to voltage by the P-channel MOS transistor PM44 and the current values of the constant-current sources of the differential amplifiers of inverters 301, 302 and 303 are varied based upon this voltage, thereby varying the delay time per inverter stage and varying the oscillation frequency. The oscillator output is delivered from the output terminal of the voltage comparator 304 to which the differential output from the inverter 303 is applied as a differential input. When the input control current Iin increases, the potential of the G terminal of inverter falls and the current that flows into the P-channel MOS transistor PM44 constituting the constant-current source of the differential pair of the inverter increases to speed up the inverting operation of the inverter. As a result, the oscillation frequency of the ring oscillator rises. When the input control current Iin decreases, on the other hand, the potential of the G terminal of inverter rises and the current that flows into the P-channel MOS transistor PM44 constituting the constant-current source of the differential pair of the inverter decreases to slow down the inverting operation of the inverter. As a result, the oscillation frequency of the ring oscillator falls.
The inverters 301–303 constructing the ring oscillator of the current-controlled oscillator may of course be constituted by clocked inverters rather than by differential circuits.
Described next will be an example of the operation of a PLL circuit for reading data out of a recording disk and synchronizing the phase of a read clock to that of input data.
FIGS. 14A and 14B are timing waveform diagrams illustrating an operation for timing input data applied to the phase comparator 10 (see FIG. 10) of the PLL circuit, the output signal (the read clock) of the frequency divider 50 (FIG. 10) and the UP and DOWN signals output from the phase comparator 10.
In the example shown in FIG. 14A, the UP signal in the phase comparator 10 makes a transition from the low to the high level in sync with the rising edge of the input data in a cycle t0 of the read clock. In the next cycle t1, the UP signal makes a transition to the low level in sync with the rising edge of the read clock rising from the low to the high level (i.e., the UP signal takes on a pulse width that corresponds to the phase lag of the read signal relative to the change in the input data). After the UP signal makes this transition to the low level, the DOWN signal rises in sync with the rising edge of the read clock in cycle t2 and then falls in sync with the falling edge of the read clock (the pulse width of the DOWN signal is that of the read clock). In cycle t3 of the read clock, the UP signal makes a transition from the low to the high level in sync with the falling edge of the input data. In cycle t4, the UP signal makes a transition to the low level in sync with the rising edge of the read clock rising from the low to the high level.
If the phases of the input data and read clock are synchronized, the pulse width of the UP signal and the pulse width of the DOWN signal will coincide and will take on the pulse width of the read clock.
In the example shown in FIG. 14B, the UP signal in the phase comparator 10 makes a transition from the low to the high level in sync with the rising edge of the input data in a cycle t0 of the read clock. In the next cycle t1, the UP signal makes a transition to the low level in sync with the falling edge of the read clock falling from the high to low high level and the DOWN signal makes a transition from the low to the high level. In cycle t2, the DOWN signal makes a transition to the low level in sync with the falling edge of the read clock. In cycle t3 of the read clock, the UP signal makes a transition from the low to the high level in sync with the falling edge of the input data. In the next cycle t4, the UP signal falls to the low level and the DOWN signal makes a transition from the low to the high level in sync with the falling edge of the read clock. In the next cycle t5, the DOWN signal falls to the low level in sync with the falling edge of the read clock.
If the phases of the input data and read clock are synchronized in the example of FIG. 14B, the pulse width of the UP signal and the pulse width of the DOWN signal will coincide and will take on one period of the read clock.